Micro Architecture "NetBurst"
Netburst is the name for Intel's new microprocessor architecture.
In order to maintain the a stability in the fast growing PC market, every
3 - 4 years Intelís develops a totally new microprocessor architecture. The
last architecture Intel released was the P6 Micro Architecture, first introduced
with the Pentium Pro back in 1995.†
The P6 architecture was a great design until we reached the 1GHz
mark at which point this design was pushing its limits on reaching higher
peaks. You might remember the famous Pentium III 1.13GHz recall that took
place last August. The reason behind this was simple, Intel pushed the P6
design to far, and stability problems immediately began.†
In November 2000, Intel officially launched their newest Architecture
named NetBurst; this was introduced with the launch of the Pentium 4 processor,
the first ever IA-32 processor to take advantage of it. NetBurst includes
the fallowing innovations.
Hyper Pipelined Technology
In order to deliver the highest clock
rates, the Pentium 4 features a pipeline twice as big as the one on the Pentium
III (10). The original Pentium processor, which was based on the P5 architecture,
featured a total of 5 stages. Intel doubled that number on the P6 architecture,
this of course covering the latest Pentium III and the first ever CPU introduced
on that architecture, the Pentium Pro which featured a total of 10 Pipelines.
Intel doubled that number again with their latest architecture (NetBurst);
the Pentium 4 features a total of 20 Pipelines. The 20 pipeline allowed Intel
to start the Pentium 4 at 1.4GHz+ using the same .18 technology that they
use to produce the Pentium III (Coppermine) Processor. With their upcoming
move to the .13 process, we will be able to see the NetBurst architecture
going beyond 2GHz. The 20-stage pipeline is what Intel calls
their Hyper Pipelined Technology.
Advanced Dynamic Execution
Intel describes the Advanced Dynamic Execution being an out of order speculative
execution engine. This Engine keeps the execution units executing instructions.
This is accomplished by providing a large window of instructions from which
the execution units can choose. The large out of order instruction window
allows the processor to avoid stalls that might occur while instructions are
waiting for dependencies to resolve. Intelís previous P6 architecture featured
a small window with 42 instructions, compared to the NetBurst architecture
that can have up to 126 instructions in this window (in flight).
This technology at the same time features an improved branch prediction capability.
The Pentium 4 is estimated to reduce branch miss-predictions by around 33%
compared to the P6 architectureís branch prediction capability. This is achieved
by implanting a 4K branch target buffer that is used to store more detail
on the history of past branches and as well as by implementing a more advanced
branch prediction algorithm.